metal layer 1 is not usable for routing, and metal layer 2 is 20 percent obstructed by vias connecting layer 1 andlayer 2. Using the ratio of horizontal-to-vertical routing resources, the best aspect ratio is 1.11 therefore, the chip aspect ratio is rectangular rather than square and is wider than it is high:.This means that the available vertical routing resource is less than the horizontal routing resource, which dictates a chip aspect ratio that is wider than it is high. If routing pitch is the same on all layers, the ratio between horizontal and vertical layers is approximately 2: 1.8. These vias tend to obstruct about 20 percent of the potential vertical routing on metal layer 2. Metal layer 2 often connects to metal layer 1 pins through vias. Usually, layer 1 is occupied by the standard cell geometries and is unusable for routing. Consider a five-layer design in which layers 1, 3, and 5 are horizontal and layers 2 and 4 are vertical. This includes buffers, which (for the purposes of computing utilization) are assumed to be placed outside of non-buffer blockage areas. The effective utilization definition is that all standard cells are placed outside of the blockage areas.Blockages, macros, and pads are combined in the denominator of the effective Utilization.If the area of macros is more than utilization can be increased accordingly. The Assumption is that the Standard Cells occupies 70 % of Base Layers and the remaining 30 % is utilized for Routing.
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